VHDL

This is intended as a personal on-line resource of VHDL code that I've found usefull. As time goes on, and I ge more experience, I'll add more to this page. More extensive on-line crib-sheets can be found at TODO. Personally I tend to prefer to have references examples of actual code.

The keyword BLOCK refers to a generic block of VHDL code.

   configuration configuration-name of entity-name is
     for architecture-name
     [
       for instance-name | all : component-name
         use configuration 

           work.name-of-config-to-be-referenced
       end for;
       ...
     ]
     end for;
   end configuration-name

Flow control

conditional

looping

CONDITIONAL

Numeric

• = < > <= >= != - for numeric.

conversions

to_stdlogicvector(std_ulogic_vectorSignal)
to_stdulogicvector(std_logic_vectorSignal)